
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
5
MK2069-01
REV K 051310
Application Information
The MK2069-01 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
RV Divider = 1,2,4 or 128
The operational frequency range of VCLK is set by the
allowable frequency range of the external VCXO crystal and
by the internal VCXO divider selections:
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
frequency range of VCLK in a given configuration is limited
to the pullable range of the crystal. This is guaranteed to be
+/-115 ppm minimum. This frequency range in ppm also
applies to the input clock and other clock outputs if the
device is to remain frequency locked to the input, which is
required for normal operation.
f(VCLK)
FV Divider
RV Divider
----------------------------
f(ICLK)
×
=
f(VCLK)
fVCXO
()
SV Divider
-----------------------
=